View AD7190_4265987.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA
Preliminary Technical Data
FEATURES
RMS Noise: 7 nV @ 4.7 Hz (gain = 128) 16.5 noise free bits @ 2.4 kHz (gain = 128) Up to 23 noise free bits (gain = 1) Offset drift: 5 nV/C Gain drift: 2 ppm/C Specified drift over time Programmable gain (1 - 128) Update rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection Four general purpose digital outputs Power supply: 3 V to 5.25 V Current: 6 mA Temperature range: -40C to +105C PLC/DCS Analog Input Modules Data Acquisition Medical and Scientific instrumentation
AD7190
GENERAL DESCRIPTION
The AD7190 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24bit - ADC. The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC. The device can be configured to have two differential inputs or four pseudo-differential inputs. The device can be operated with either the internal clock or an external clock. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz. The device can be operated with a sinc3 or a sinc4 digital filter. At the lower update rates, the sinc3 is useful to optimize the settling time. The benefit of the sinc4 at low update rates is the superior 50 Hz/60 Hz rejection. At the higher update rates, the sinc4 filter gives best noise performance. For applications that require all conversions to be settled, the AD7190 includes a zero-latency feature. The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 6 mA. It is housed in a 24-lead TSSOP package.
INTERFACE
3-wire serial SPI(R), QSPITM, MICROWIRETM, and DSP compatible Schmitt trigger on SCLK
APPLICATIONS
Weigh scales Strain gauge transducers Pressure measurement Temperature measurement Chromatography
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND REFIN1(+) REFIN1(-)
AD7190
AVDD AIN1 AIN2 AIN3 AIN4 AINCOM MUX PGA SIGMA DELTA ADC
REFERENCE DETECT
SERIAL INTERFACE AND CONTROL LOGIC
DOUT/RDY DIN SCLK CS
BPDSW
AGND TEMP SENSOR AGND MCLK1 MCLK2 P0/REFIN2(-) P1/REFIN2(+) CLOCK CIRCUITRY
SYNC P3 P2
Figure 1.
Rev.PrD
7/08 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2008 Analog Devices, Inc. All rights reserved.
AD7190 SPECIFICATIONS
Preliminary Technical Data
AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; REFIN1(+) = AVDD ; REFIN1(-) = GND; MCLK = 4.9152 MHz; Sinc4 filter selected; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter1
Output Update Rate No Missing Codes2 Resolution
AD7190B
4.7 to 4800 1.17 to 1200 24 See RMS Noise and
Unit
Hz nom Hz nom Bits min
Test Conditions/Comments
Chop Disabled Chop Enabled FS > 1
RMS Noise and Update Rates
Resolution Specifications See RMS Noise and Resolution Specifications
15 100/Gain 0.5 150/Gain 10 5 25 10 1 10 100 VREF/gain (AVDD - 1V)/gain ppm of FSR max V typ V typ nV/C typ nV/C typ nV/C typ nV/1000 Hours typ V typ ppm/C typ ppm/1000 Hours typ dB min V nom V min/max V min V max V min V max Chop Disabled Chop Enabled Gain = 1 to 16. Chop Disabled Gain = 32 to 128. Chop Disabled Chop Enabled
Integral Nonlinearity Offset Error3 Offset Error Drift vs. Temperature4
Offset Error Drift vs. Time Full-Scale Error3, 5 Gain Drift vs. Temperature4 Gain Drift vs. Time Power Supply Rejection ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode Analog Input Current Buffered Mode Input Current2 Input Current Drift Unbuffered Mode Input Current Input Current Drift Normal Mode Rejection2 @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz Common-Mode Rejection @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 REFERENCE INPUT REFIN Voltage
VIN = 1 V/Gain. 120 dB typical. VREF = REFIN(+) - REFIN(-) , gain = 1 to 128 gain > 1
GND - 50 mV AVDD + 50 mV GND + 200 mV AVDD - 200 mV
1 3 2 5 1 50 98 TBD TBD TBD 100 100 100
nA max nA typ pA/C typ A/V typ A/V typ pA/V/C typ dB min dB min dB min dB min dB min dB min dB min
Gain = 1 Gain > 1
Gain = 1. Input current varies with input voltage Gain > 1.
10 Hz Update Rate, 50 1 Hz, 60 1 Hz 50 Hz Update Rate, REJ606 = 1, 50 1 Hz, 60 1 Hz 50 Hz Update Rate, 50 1 Hz 60 Hz Update Rate, 60 1 Hz AIN = 1 V/gain 10 Hz Update Rate, 50 1 Hz, 60 1 Hz 50 1 Hz (50 Hz Update Rate), 60 1 Hz (60 Hz Update Rate) REFIN = REFIN(+) - REFIN(-)
AVDD
V nom
Rev.PrD 7/08 | Page 2
Preliminary Technical Data
Parameter1
Reference Voltage Range2
AD7190
Unit
V min V max V min V max A/V typ nA/V/C typ
AD7190B
1 AVDD GND - 50 mV AVDD + 50 mV 6 0.03 Same as for analog inputs 100 0.3 0.5 +2 2800 7 9 30 500 AVDD - 0.6 0.4 4 0.4 10 10
Test Conditions/Comments
The differential input must be limited to (AVDD - 1V)/gain when gain > 1
Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Normal Mode Rejection2 Common-Mode Rejection Reference Detect Levels TEMPERATURE SENSOR Accuracy Sensitivity LOW SIDE POWER SWITCH RON Allowable Current2 BURNOUT CURRENTS AIN Current DIGITAL OUTPUTS (P0 - P3) VOH, Output High Voltage2 VOL, Output Low Voltage
2
dB typ
V min V max C typ codes/C typ max max mA max nA nom V min V max V min V max A max pF typ AVDD = 3V, ISOURCE = 100 A AVDD = 3V, ISINK = 100 A AVDD = 5V, ISOURCE = 200 A AVDD = 5V, ISINK = 800 A Applies after user-calibration at one temperature
AVDD = 5 V AVDD = 3 V Continuous Current
VOH, Output High Voltage2 VOL, Output Low Voltage2 Floating-State Leakage Current Floating-State Output Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency Duty Cycle External Clock/Crystal Frequency VINL, Input Low Voltage VINH, Input High Voltage Input Current LOGIC INPUTS VT(+) VT(-) VT(+) - VT(-) VT(+) VT(-) VT(+)- VT(-) Input Currents LOGIC OUTPUT (DOUT/RDY) VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2
4.92 + 4% 50:50 4.9152 2.4576/5.12 0.8 0.4 2.5 3.5 10 1.4/2 0.8/1.7 0.1/0.17 0.9/2 0.4/1.35 0.06/0.13 10 DVDD - 0.6 0.4 4
MHz min/max % typ MHz nom MHz min/max V max V max V min V min A max V min/V max V min/V max V min/V max V min/V max V min/V max V min/V max A max V min V max V min
Rev.PrD 7/08 | Page 3
DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 5 V MCLKIN = DVDD or GND DVDD = 5 V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 3 V VIN = DVDD or GND DVDD = 3 V, ISOURCE = 100 A DVDD = 3 V, ISINK = 100 A DVDD = 5 V, ISOURCE = 200 A
AD7190
Parameter1
VOL, Output Low Voltage2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS7
Preliminary Technical Data
AD7190B
0.4 10 10 Offset binary 1.05 x FS -1.05 x FS 0.8 x FS 2.1 x FS
Unit
V max A max pF typ
Test Conditions/Comments
DVDD = 5 V, ISINK = 1.6 mA
V max V min V min V max
Power Supply Voltage AVDD - AGND DVDD - DGND Power Supply Currents AIDD Current
3/5.25 2.7/5.25 TBD TBD TBD TBD TBD TBD 1 1
V min/max V min/max mA max mA max mA max mA max mA max mA max mA max A max Gain = 1, Buffer off Gain = 8, Buffer off Gain = 8, Buffer on Gain = 16 - 128, Buffer off Gain = 16 - 128, Buffer on DVDD = 3 V DVDD = 5 V
DIDD Current IDD (Power-Down Mode)
1 2
Temperature range: -40C to +105C. Specification is not production tested but is supported by characterization data at initial product release. 3 Following a calibration, this error will be in the order of the noise for the programmed gain and update rate selected. 4 Recalibration at any temperature will remove these errors. 5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 5 V, gain = 1, TA = 25C). 6 REJ60 is a bit in the Mode Register. When the update rate is set to 50 Hz, setting REJ60 to `1' places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection. 7 Digital inputs equal to DVDD or GND.
Rev.PrD 7/08 | Page 4
Preliminary Technical Data TIMING CHARACTERISTICS
AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2.
Parameter1, 2 t3 t4 Read Operation t1 Limit at TMIN, TMAX (B Version) 100 100 0 60 80 0 60 80 10 80 0 10 0 30 25 0 Unit ns min ns min ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min ns min ns min ns min ns min Conditions/Comments SCLK high pulse width SCLK low pulse width CS falling edge to DOUT/RDY active time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK active edge to data valid delay4 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus relinquish time after CS inactive edge SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time
AD7190
t23
t55, 6 t6 t7 Write Operation t8 t9 t10 t11
1 2
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.
ISINK (1.6mA WITH DVDD = 5V, 100A WITH DVDD = 3V)
TO OUTPUT PIN 50pF
1.6V
ISOURCE (200A WITH DVDD = 5V, 100A WITH DVDD = 3V)
Figure 2. Load Circuit for Timing Characterization
Rev.PrD 7/08 | Page 5
04854-002
AD7190
TIMING DIAGRAMS
Preliminary Technical Data
CS (I)
t1
DOUT/RDY (O) MSB LSB
t6 t5
t2 t3
SCLK (I)
t7
t4
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
CS (I)
t8
SCLK (I)
t11
t9 t10
DIN (I) MSB LSB
04854-004
I = INPUT, O = OUTPUT
Figure 4. Write Cycle Timing Diagram
Rev.PrD 7/08 | Page 6
04854-003
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter AVDD to GND DVDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND AIN/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature TSSOP JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +6.5 V -0.3 V to +6.5 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to DVDD + 0.3 V 10 mA -40C to +105C -65C to +150C 150C 97.9C/W 14C/W 215C 220C
AD7190
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev.PrD 7/08 | Page 7
AD7190 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
MCLK1 1 MCLK2 2 SCLK 3 CS 4 P3 5 P2 6 P1/REFIN2(+) 7 P0/REFIN2(-) 8 NC 9 AINCOM 10 AIN1 11 AIN2 12 24 DIN 23 DOUT/RDY 22 SYNC 21 DVDD AD7190 TOP VIEW 20 AVDD (Not To 19 DGND Scale) 18 AGND 17 BPDSW 16 REFIN1(-) 15 REFIN1(+) 14 AIN4 13 AIN3
Preliminary Technical Data
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 Mnemonic MCLK1 MCLK2 Description When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. Master Clock signal for the device. The AD7190 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7190 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOScompatible clock and MCLK1 left unconnected. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. Digital Output Pin. This pin can function as a general purpose output bit referenced between AVDD and AGND. Digital Output Pin. This pin can function as a general purpose output bit referenced between AVDD and AGND. Digital Output Pin/Positive Reference Input. This pin functions as a general purpose output bit referenced between AVDD and AGND. When REFSEL = 1, this pin functions as REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(-). REFIN2(+) can lie anywhere between AVDD and GND + 1 V. The nominal reference voltage, (REFIN2(+) - REFIN2(-)), is AVDD, but the part functions with a reference from 1 V to AVDD. Digital Output Pin/Negative Reference Input. This pin functions as a general purpose output bit referenced between AVDD and AGND. When REFSEL = 1, this pin functions as REFIN2(-). This reference input can lie anywhere between GND and AVDD - 1 V. No Connect. This pin should be tied to AGND. Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudo-differential operation. Analog Input. It can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudo-differential input when used with AINCOM. Analog Input. It can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudo-differential input when used with AINCOM. Analog Input. It can be configured as the positive input of a fully differential input pair when used with
Rev.PrD 7/08 | Page 8
3
SCLK
4
CS
5 6 7
P3 P2 P1/REFIN2(+)
8
P0/REFIN2(-)
9 10 11 12 13
NC AINCOM AIN1 AIN2 AIN3
Preliminary Technical Data
Pin No. 14 15 Mnemonic AIN4 REFIN1(+)
AD7190
16 17 18 19 20 21 22
REFIN1(-) BPDSW AGND DGND AVDD DVDD SYNC
23
DOUT/RDY
24
DIN
Description AIN4 or as a pseudo-differential input when used with AINCOM. Analog Input. It can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudo-differential input when used with AINCOM. Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(-). REFIN1(+) can lie anywhere between AVDD and GND + 1 V. The nominal reference voltage, (REFIN1(+) - REFIN1(-)), is AVDD, but the part functions with a reference from 1 V to AVDD. Negative Reference Input. This reference input can lie anywhere between GND and AVDD - 1 V. Low Side Power Switch to AGND. Analog Ground Reference Point. Digital Ground Reference Point. Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore DVDD can be operated at 3 V with AVDD at 5 V or vice versa. Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore AVDD can be operated at 3 V with DVDD at 5 V or vice versa. Logic Input that allows for synchronization of the digital filters and analog modulators when using a number of AD7190 devices. While SYNC is low, the nodes of the digital filter, the filter control logic and the calibration control logic are reset and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull- up resistor internally to DVDD. Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDYoperates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin will go high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers within the ADC, the register selection bits of the communications register identifying the appropriate register.
Rev.PrD 7/08 | Page 9
AD7190 RMS NOISE AND RESOLUTION SPECIFICATIONS
The AD7190 can be operated with chop enabled or chop disabled. With chop enabled, the settling time is two times the conversion time. The offset is continuously removed by the ADC leading to low offset and low offset drift. With chop disabled, higher update rates can be achieved from the ADC. The settling time is three times (sinc3) or four times (sinc4) the selected update rate. With chop disabled, the offset is not removed by the ADC. The offset and offset drift is comparable between chop enabled and chop disabled for gains of 32 or higher. For lower gains, however, periodic offset calibrations may be required to remove offset due to drift.
Preliminary Technical Data
CHOP DISABLED
Table 5 shows the rms noise of the AD7190 for some of the update rates and gain settings with chop disabled. The numbers given are for the bipolar input range with the external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 6 shows the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets. It is important to note that the effective resolution is calculated using the rms noise, while the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there will be no code flicker. These numbers are typical and are rounded to the nearest half-LSB.
SINC4 FILTER
The sinc4 filter optimizes the 50 Hz/60 Hz rejection. At the higher update rates, it also gives better rms noise performance compared with the sinc3 filter.
Table 5. RMS Noise (nV) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Disabled
Filter Word (Decimal) 1023 640 480 96 16 2 1 Update Rate (Hz) 4.7 7.5 10 50 300 2400 4800 Gain of 1 174 196 246 558 1344 4254 13000 Gain of 8 24.71 30.28 38 87 186 582 1776 Gain of 16 12.65 14.52 19.33 44 105 322 900 Gain of 32 10 12.28 14.14 35.66 72.82 232 678 Gain of 64 8.3 10.37 12.00 27.78 68.57 200 497 Gain of 128 7 9.5 10.26 25.3 52.66 167 376
Table 6. Typical Resolution (Bits) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Disabled
Filter Word (Decimal) 1023 640 480 96 16 2 1 Update Rate (Hz) 4.7 7.5 10 50 300 2400 4800 Gain of 1 24 (23) 24 (23) 24 (22.5) 24 (21.5) 23(20.5) 21 (18.5) 19.5 (17) Gain of 8 24 (23) 24 (22.5) 24 (22.5) 24 (21.5) 22.5 (20) 21 (18.5) 19.5 (17) Gain of 16 24 (23) 24 (22.5) 24 (22) 24 (21.5) 22.5 (20) 21 (18.5) 19.5 (17) Gain of 32 24 (22) 24 (22) 24 (21.5) 23 (20.5) 22 (19.5) 20.5 (18) 19 (16.5) Gain of 64 24 (21.5) 24 (21.5) 23.5 (21) 22.5 (20) 21 (18.5) 19.5 (17) 18 (15.5) Gain of 128 23.5 (21) 23 (20.5) 23 (20.5) 21.5 (19) 20.5 (18) 19 (16.5) 17.5 (15)
Rev.PrD 7/08 | Page 10
Preliminary Technical Data
CHOP ENABLED
Table 7 shows the AD7190's rms noise for some of the update rates and gain settings. The numbers given are for the bipolar input range with an external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 8 shows the effective resolution, while the output peak-topeak (p-p) resolution is listed in brackets. It is important to note
AD7190
that the effective resolution is calculated using the rms noise, while the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there will be no code flicker. These numbers are typical and are rounded to the nearest half-LSB.
Table 7. RMS Noise (nV) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Enabled
Filter Word (Decimal) 1023 640 480 96 16 2 1 Update Rate (Hz) 1.175 1.875 2.5 12.5 75 600 1200 Gain of 1 123 138 174 395 950 3008 9192 Gain of 8 17.47 21.41 26.87 61.52 132 412 1255 Gain of 16 8.94 10.27 13.67 31.11 74.25 228 636 Gain of 32 7.07 8.68 10 25.22 51.5 164 479 Gain of 64 5.87 7.33 8.49 19.64 48.49 141 351 Gain of 128 5 7.07 7.25 17.9 37.24 118 266
Table 8. Typical Resolution (Bits) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Enabled
Filter Word (Decimal) 1023 640 480 96 16 2 1 Update Rate (Hz) 1.175 1.875 2.5 12.5 75 600 1200 Gain of 1 24 (23.5) 24 (23.5) 24 (23) 24 (22) 23.5 (21) 21.5 (19) 20 (17.5) Gain of 8 24 (23.5) 24 (23) 24 (22.5) 24 (21.5) 23 (20.5) 21.5 (19) 20 (17.5) Gain of 16 24 (23.5) 24 (23) 24 (22.5) 24 (21.5) 23 (20.5) 21.5 (19) 20 (17.5) Gain of 32 24 (22.5) 24 (22.5) 24 (22) 23.5 (21) 22.5 (20) 21 (18.5) 19.5 (17) Gain of 64 24 (22) 24 (21.5) 24 (21.5) 23 (20.5) 21.5 (19) 20 (17.5) 18.5 (16) Gain of 128 24 (21.5) 23.5 (21) 23 (20.5) 22 (19.5) 21 (18.5) 19.5 (17) 18 (15.5)
Rev.PrD 7/08 | Page 11
AD7190
SINC3 FILTER
For a given update rate, the sinc3 filter has lower settling time than the sinc3 filter. At low update rates, the rms noise is comparable between the sinc3 filter and the sinc4 filter. So, the user can optimize the settling time without compromising the rms noise. At high update rates, the sinc4 filter is needed for optimum performance of the AD7190.
Preliminary Technical Data
numbers given are for the bipolar input range with the external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 10 shows the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets. It is important to note that the effective resolution is calculated using the rms noise, while the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there will be no code flicker. These numbers are typical and are rounded to the nearest half-LSB.
CHOP DISABLED
Table 9 shows the rms noise of the AD7190 for some of the update rates and gain settings with chop disabled. The
Table 9. RMS Noise (nV) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Disabled
Filter Word (Decimal) 1023 640 480 96 16 2 1 Update Rate (Hz) 4.7 7.5 10 50 300 2400 4800 Gain of 1 177 200 276 606 1400 57510 438100 Gain of 8 26.5 31 41 93 205 7000 54690 Gain of 16 13.22 16.12 20.48 48 112 3570 27340 Gain of 32 10.52 13.13 15.42 36.92 84 1770 14220 Gain of 64 8.7 10.97 12.82 29.68 73.21 896 6890 Gain of 128 7.68 10.02 10.74 25.66 60 464 3480
Table 10. Typical Resolution (Bits) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Disabled
Filter Word (Decimal) 1023 640 480 96 16 2 1 Update Rate (Hz) 4.7 7.5 10 50 300 2400 4800 Gain of 1 24 (23) 24 (23) 24 (22.5) 24 (21.5) 23(20.5) 17.5 (15) 14.5 (12) Gain of 8 24 (23) 24 (22.5) 24 (22) 23.5 (21) 22.5 (20) 17.5 (15) 14.5 (12) Gain of 16 24 (23) 24 (22.5) 24 (22) 23.5 (21) 22.5 (20) 17.5 (15) 14.5 (12) Gain of 32 24 (22) 24 (22) 24 (21.5) 23 (20.5) 22 (19.5) 17.5 (15) 14.5 (12) Gain of 64 24 (21.5) 24 (21.5) 23.5 (21) 22.5 (20) 21 (18.5) 17.5 (15) 14.5 (12) Gain of 128 23.5 (21) 23 (20.5) 23 (20.5) 21.5 (19) 20.5 (18) 17.5 (15) 14.5 (12)
Rev.PrD 7/08 | Page 12
Preliminary Technical Data
CHOP ENABLED
Table 11 shows the AD7190's rms noise for some of the update rates and gain settings. The numbers given are for the bipolar input range with an external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 12 shows the effective resolution, while the output peakto-peak (p-p) resolution is listed in brackets. It is important to
AD7190
note that the effective resolution is calculated using the rms noise, while the p-p resolution is calculated based on peak-topeak noise. The p-p resolution represents the resolution for which there will be no code flicker. These numbers are typical and are rounded to the nearest half-LSB.
Table 11. RMS Noise (nV) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Enabled
Filter Word (Decimal) 1023 640 480 96 16 2 1 Update Rate (Hz) 1.56 2.5 3.33 16.6 100 800 1600 Gain of 1 125 173 195 429 990 40666 309783 Gain of 8 18.74 21.92 29 66 145 4950 38672 Gain of 16 9.35 11.4 14.48 34 79.2 2524 19332 Gain of 32 7.44 9.28 10.90 26.11 59.4 1252 10055 Gain of 64 6.15 7.76 9.06 20.99 51.77 634 4872 Gain of 128 5.43 7.09 7.59 18.14 44.62 328 2461
Table 12. Typical Resolution (Bits) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Enabled
Filter Word (Decimal) 1023 640 480 96 16 2 1 Update Rate (Hz) 1.56 2.5 3.33 16.6 100 800 1600 Gain of 1 24 (23.5) 24 (23.5) 24 (23) 24 (22) 23.5 (21) 18 (15.5) 15 (12.5) Gain of 8 24 (23.5) 24 (23) 24 (22.5) 24 (21.5) 23 (20.5) 18 (15.5) 15 (12.5) Gain of 16 24 (23.5) 24 (23) 24 (22.5) 24 (21.5) 23 (20.5) 18 (15.5) 15 (12.5) Gain of 32 24 (22.5) 24 (22.5) 24 (22) 23.5 (21) 22.5 (20) 18 (15.5) 15 (12.5) Gain of 64 24 (22) 24 (21.5) 24 (21.5) 23 (20.5) 21.5 (19) 18 (15.5) 15 (12.5) Gain of 128 24 (21.5) 23.5 (21) 23 (20.5) 22 (19.5) 21 (18.5) 18 (15.5) 15 (12.5)
Rev.PrD 7/08 | Page 13
AD7190 TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
Figure 6.
Figure 9.
Figure 7.
Figure 10.
Figure 8. Figure 11.
Rev.PrD 7/08 | Page 14
Preliminary Technical Data ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted.
AD7190
write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 40 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 13 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in brackets indicates the poweron/reset default status of that bit.
COMMUNICATIONS REGISTER
(RS2, RS1, RS0 = 0, 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or
CR7 WEN(0)
CR6 R/W(0)
CR5 RS2(0)
CR4 RS1(0)
CR3 RS0(0)
CR2 CREAD(0)
CR1 0(0)
CR0 0(0)
Table 13. Communications Register Bit Designations
Bit Location CR7 Bit Name WEN Description Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the communications register. A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this position indicates that the next operation will be a read from the designated register. Register Address Bits. These address bits are used to select which registers of the ADC are being selected during this serial interface communication. See Table 14. Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read, that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, the instruction 01011100 must be written to the communications register. To disable continuous read, the instruction 01011000 must be written to the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset will occur if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low until an instruction is to be written to the device. These bits must be programmed to Logic 0 for correct operation.
CR6 CR5 to CR3 CR2
R/W RS2 to RS0 CREAD
CR1 to CR0
0
Table 14. Register Selection
RS2 0 0 0 0 0 1 1 1 1 RS1 0 0 0 1 1 0 0 1 1 RS0 0 0 1 0 1 0 1 0 1 Register Communications Register During a Write Operation Status Register During a Read Operation Mode Register Configuration Register Data Register / Data Register + Status Information ID Register GPOCON Register Offset Register Full-Scale Register Register Size 8-bit 8-bit 24-bit 24-bit 24-bit / 32-bit 8-bit 8-bit 24-bit 24-bit
Rev.PrD 7/08 | Page 15
AD7190
STATUS REGISTER
(RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80)
Preliminary Technical Data
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 15 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
SR7 RDY(1) SR6 ERR(0) SR5 NOREF(0) SR4 PARITY(0) SR3 CHD3(0) SR2 CHD2(0) SR1 CHD1(0) SR0 CHD0(0)
Table 15. Status Register Bit Designations
Bit Location SR7 Bit Name RDY Description Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode, idle mode or when SYNC is taken low. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange, or the absence of a reference voltage. Cleared by a write operation to start a conversion. No External Reference Bit. Set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all ones. Cleared to indicate that a valid reference is applied to the selected reference pins. The NOXREF bit is enabled by setting the REF_DET bit in the configuration register to 1. The ERR bit is also set if the voltage applied to the selected reference input is invalid. Parity Check of Data Register. If the ENPAR bit is set, the PARITY bit is set if there is an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. These bits indicate which channel corresponds to the data register contents. They do not indicate which channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was being generated.
SR6
ERR
SR5
NOREF
SR4
PARITY
SR3 to SR0
CHD3 to CHD0
MODE REGISTER
(RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060)
The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the update rate, and the clock source. Table 16 outlines the bit designations for the mode register. MR0 through MR23 indicate the bit locations, MR denoting the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and filter and sets the RDY bit.
MR23 MD2(0) MR15 SINC3(0) MR7 FS7(0) MR22 MD1(0) MR14 0 MR6 FS6(1) MR21 MD0(0) MR13 ENPAR(0) MR5 FS5(1) MR20 DAT_STA(0) MR12 0 MR4 FS4(0) MR19 CLK1(1) MR11 SINGLE(0) MR3 FS3(0) MR18 CLK0(0) MR10 REJ60(0) MR2 FS2(0) MR17 0 MR9 FS9(0) MR1 FS1(0) MR16 0 MR8 FS8(0) MR0 FS0(0)
Table 16. Mode Register Bit Designations
Bit Location MR23 to MR21 MR20 Bit Name MD2 to MD0 DAT_STA Description Mode Select Bits. These bits select the operational mode of the AD7190 (see Table 17). Transmit status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register
Rev.PrD 7/08 | Page 16
Preliminary Technical Data
Bit Location Bit Name
AD7190
MR19 to MR18
CLK1 to CLK0
MR17 to MR16 MR15
0 SINC3
MR14 MR13
0 ENPAR
MR12 MR11
0 SINGLE
MR10
REJ60
MR9 to MR0
FS9 to FS0
Description read. This function is useful when several channels are selected as the status register identifies the channel to which the data register value corresponds. These bits are used to select the clock source for the AD7190. Either the on-chip 4.92 MHz clock can be used or an external clock can be used. The ability to use an external clock allows several AD7190 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7190. CLK1 CLK0 ADC Clock Source 0 0 External crystal used. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock used. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tri-stated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2. These bits must be programmed with a Logic 0 for correct operation. Sinc3 Filter Select pin. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set, a sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time when chop is disabled. For a given update rate fADC, the sinc3 filter has a settling time of fADC/3 while the sinc4 filter has a settling time of fADC/4. The sinc4 filter, due to its deeper notches, gives better 50 Hz/60 Hz rejection. At low update rates, both filters give similar rms noise and similar no missing codes for a given update rate. At higher update rates (FS values less than 5), the sinc4 filter gives better performance than the sinc3 filter for rms noise and no missing codes. This bit must be programmed with a Logic 0 for correct operation. Enable Parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. This bit must be programmed with a Logic 0 for correct operation. Single Cycle Conversion Enable Bit. When this bit is set, the AD7190 allows the complete settling time to perform each conversion. So, the device functions as a zero-latency ADC. Enables a notch at 60 Hz when the update rate is equal to 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the update rate selected is 50 Hz. This allows simultaneous 50 Hz/60 Hz rejection. Filter Update Rate Select Bits. The 10 bits of data programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter and the data rate for the part. In association with the gain selection, it also determines the output noise (and hence the effective resolution) of the device. When chop is disabled and continuous conversion mode is selected, the first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (fmod/64)/FS where FS is the decimal equivalent of the code in bits FS0 to FS9 and is in the range 1 to 1023 and fmod is the modulator frequency which is equal to MCLK/16. With the nominal MCLK of 4.92 MHz, this results in a first notch frequency range from 4.69 Hz to 4.8 kHz. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables 5 through 8 show the effect of the filter notch frequency and gain on the effective resolution of the AD7190. The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 1.2 kHz, a new word is available every 0.83 ms. The settling time of the filter to a full-scale step input change is worst case (N + 1)/(output data rate) where N = 3 when the sinc3 filter is selected and N = 4 when the sinc4 filter is selected. For example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is 100 ms max when N = 4. This settling time can be reduced to N/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with the SYNC input low, the settling time will be N/(output data rate) from when SYNC returns high. If a change of channel takes place, the settling time is N/(output data rate) regardless of the SYNC status as the part issues an internal reset command when requested to change channels. The -3 dB frequency is determined by the programmed first notch frequency according to the
Rev.PrD 7/08 | Page 17
AD7190
Bit Location Bit Name
Preliminary Technical Data
Description relationship: filter -3 dB frequency = 0.23 x filter first notch frequency. When chop is enabled, the conversion time equals Conversion rate = (fmod/64)/(NxFS) where FS is the decimal equivalent of the code in bits FS0 to FS9 and is in the range 1 to 1023 and fmod is the modulator frequency which is equal to MCLK/16. With the nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz where N is the order of the sinc filter. The first notch in the frequency response is placed at conversion rate/2. The settling time is equal to 2 x conversion time.
Table 17. Operating Modes
MD2 0 MD1 0 MD0 0 Mode Continuous Conversion Mode (Default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to `1' which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset or a re-configuration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected update rate which is dependent on filter choice. Single Conversion Mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion which requires the complete settling time of the filter. The conversion result is placed in the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed. Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. Power-Down Mode. In power-down mode, all the AD7190 circuitry, except the power switch, is powered down. The power switch remains active as the user may need to power up the sensor prior to powering up the AD7190 for settling reasons. The external crystal, if present, is left active. Internal Zero-Scale Calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. Internal Full-Scale Calibration. A full-scale input voltage is automatically connected to the input for this calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error. System Zero-Scale Calibration. User should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. System Full-Scale Calibration. User should connect the system full-scale input to the channel input pins as selected by the CH7-CH0 bits. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed.
0
0
1
0 0
1 1
0 1
1
0
0
1
0
1
1
1
0
1
1
1
Rev.PrD 7/08 | Page 18
Preliminary Technical Data
CONFIGURATION REGISTER
(RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117)
AD7190
The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and select the analog input channel. Table 18 outlines the bit designations for the filter register. CON0 through CON23 indicate the bit locations. CON denotes that the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
CON23 CHOP(0) CON15 CH7(0) CON7 BURN(0) CON22 0(0) CON14 CH6(0) CON6 REFDET(0) CON21 0(0) CON13 CH5(0) CON5 0(0) CON20 REFSEL(0) CON12 CH4(0) CON4 BUF(1) CON19 0(0) CON11 CH3(0) CON3 U/B (0) CON18 0(0) CON10 CH2(0) CON2 GN2(1) CON17 0(0) CON9 CH1(0) CON1 GN1(1) CON16 (0) CON8 CH0(1) CON0 GN0(1)
Table 18. Configuration Register Bit Designations
Bit Location CON23 Bit Name CHOP Description Chop Enable Bit. When CHOP is cleared, chop is disabled. When CHOP is set, chop is disabled. When chop is enabled, the offset and offset drift is continuously removed by the ADC. However, it increases the conversion time and settling time of the ADC. For example, when FS = 96 decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an SF word of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. These bits must be programmed with a Logic 0 for correct operation. Reference Select Bits. The reference source for the ADC is selected using these bits. REFSEL Reference Voltage 0 External reference applied between REFIN1(+) and REFIN1(-) 1 External reference applied between the P1 and P0 pins. These bits must be programmed with a Logic 0 for correct operation. Channel Select Bits. These bits are used to select which channels are enabled on the AD7190. See Table 19. Several channels can be selected and the AD7190 will automatically sequence between them. The conversion on each channel will require the complete settling time. When this bit is set to 1 by the user, the 500 nA current sources in the signal path are enabled. When BURN = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active. Enables the Reference Detect Function. When set, the NOXREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.5 V. This bit must be programmed with a Logic 0 for correct operation. Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below GND to 50 mV above AVDD. When the buffer is enabled, it requires some headroom so the voltage on any input pin must be limited to 200 mV within the power supply rails.
Rev.PrD 7/08 | Page 19
CON22, CON21 CON20
0 REFSEL
CON19 to CON16 CON15 to CON8
0 CH7 to CH0
CON7
BURN
CON6
REFDET
CON5 CON4
0 BUF
AD7190
Bit Location CON3 Bit Name U/B Description Polarity Select bit. When this bit is set, unipolar operation is selected. When this but is cleared, bipolar operation is selected. Gain Select Bits. Written by the user to select the ADC input range as follows: G2 G1 G0 Gain 0 0 0 1 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128
Preliminary Technical Data
CON2 to CON0
G2 to G0
ADC Input Range (5 V Reference) 5V
625 mV 312.5 mV 156.2 mV 78.125 mV 39.06 mV
Table 19. Channel Selection
CH7 X X X X X X X 1 CH6 X X X X X X 1 X CH5 X X X X X 1 X X CH4 X X X X 1 X X X CH3 X X X 1 X X X X CH2 X X 1 X X X X X CH1 X 1 X X X X X X CH0 1 X X X X X X X Channel AIN1 - AIN2 AIN3 - AIN4 Temp Sensor AIN2 - AIN2 AIN1 - AINCOM AIN2 - AINCOM AIN3 - AINCOM AIN4 - AINCOM CHD[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Calibration Pair 0 1 None 0 0 1 2 3
DATA REGISTER
(RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000)
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set. The AD7190 can be configured for 24-bit transfers or 32-bit transfers. When 24-bit transfers are selected, the 24-bit data conversion is transmitted. When 32-bit transfers are selected, the 24-bit conversion is followed by the contents of the status register. When several channels are enabled, the ADC will automatically step between channels. So, 32-bit transmissions are required so that the user can identify the channel from which the conversions originated.
GPOCON REGISTER
(RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00)
The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the general purpose digital outputs. Table 20 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are in the GPOCON register. GP7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
GP7 0(0) GP6 BPDSW(0) GP5 GP32EN(0) GP4 GP10EN(0) GP3 P3DAT(0) GP2 P2DAT(0) GP1 P1DAT(0) GP0 P0DAT(0)
Rev.PrD 7/08 | Page 20
Preliminary Technical Data
Table 20. Register Bit Designations
Bit Location GP7 GP 6 Bit Name 0 BPDSW
AD7190
GP5
GP32EN
GP4
GP10EN
GP3 GP2 GP1 GP0
P3DAT P2DAT P1DAT P0DAT
Description This bit must be programmed with a Logic 0 for correct operation. Power Switch Control Bit. Set by user to close the power switch BPDSW to AGND. The power switch can sink up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in powerdown mode, the power switch remains active. Digital Outputs P3 and P2 Enable. When GP32EN is set, the digital outputs P3 and P2 are active. When GP32EN is cleared, the pins P3 and P2 are tri-stated and bits P3DAT and P2DAT are ignored. Digital Outputs P1 and P0 Enable. When GP10EN is set, the digital outputs P1 and P0 are active. When GP10EN is cleared, the P1 and P0 outputs are tri-stated and bits P1DAT and P0DAT are ignored. The pins P1 and P0 can be used as a reference input REFIN2 when bit REFSEL in the configuration register is set to 1. Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the general purpose output pin P3. When P3DAT is high, the output P3 is high. When P3DAT is low, the output P3 is low. Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the general purpose output pin P2. When P2DAT is high, the output P2 is high. When P2DAT is low, the output P2 is low. Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the general purpose output pin P1. When P1DAT is high, the output P1 is high. When P1DAT is low, the output P1 is low. Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the general purpose output pin P0. When P0DAT is high, the output P0 is high. When P0DAT is low, the output P0 is low.
OFFSET REGISTER
(RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000)
The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7190 has four offset registers so each channel has a dedicated offset register. Each of these registers is a 24-bit read/write register. This register is used in conjunction with its associated full-scale register to form a register pair. The poweron reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7190 must be placed in power-down mode or idle mode when writing to the offset register.
FULL-SCALE REGISTER
(RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0)
The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD7190 has 4 fullscale registers so each channel has a dedicated full-scale register. The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power-down mode or idle mode. These registers are configured on power-on with factory-calibrated full-scale calibration coefficients, the calibration being performed at gain = 1. Therefore, every device will have different default coefficients. The default value will be automatically overwritten if an internal or system full-scale calibration is initiated by the user or the full-scale register is written to.
Rev.PrD 7/08 | Page 21
PR07640-0-7/08(PrD)

▲Up To Search▲

Price & Availability of AD7190

	To Download AD7190 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .